The present invention relates to a semiconductor device having an improved trench isolation structure and a method for forming the same.
Trench isolation technique has been well known in the art as being effective to isolate two semiconductor devices formed on a common substrate. Typical one of the conventional trench isolation structures in the semiconductor devices will be described with reference to FIG. 1 which illustrates p-channel and n-channel MOS field effect transistors formed on a single semiconductor substrate 1. The single semiconductor substrate 1 is made of silicon doped with a p-type impurity. The p-channel and n-channel MOS field effect transistors are isolated by a trench isolation 11, wherein the p-channel MOS field effect transistor is provided at a left side of the trench isolation 11 whilst the n-channel MOS field effect transistor is provided at a right side of the trench isolation 11. The p-channel MOS field effect transistor is formed in an n-well region 31 formed over the semiconductor substrate 1 and at the left side of the trench isolation 11. The n-channel MOS field effect transistor is formed in a p-well region 30 formed over the semiconductor substrate 1 and at the right side of the trench isolation 11. The p-channel and n-channel MOS field effect transistors is provided to form a complementary MOS circuit. Field oxide films 5 are selectively formed to define active regions in the n-well and p-well regions 31 and 30. Gate oxide films 16 are formed on the active regions in the n-well and p-well regions 31 and 30. In the surface of the n-well region 31, p-type source/drain diffusion regions 34 are formed to define a channel region interposed between them. In the surface of the p-well region 30, n-type source/drain diffusion regions 33 are formed to define a channel region interposed between them. Gate electrodes 32 are provided on the gate oxide films 16 over the n-well and p-well regions 31 and 30 respectively.
The trench isolation 11 extends in a vertical direction from the field oxide film 5 to an upper region of the p-type semiconductor substrate 1 so as to completely isolate the n-well and p-well regions 31 and 30. The trench isolation region 11 comprises a trench groove, an insulation layer formed on inner walls of the trench groove and a polysilicon material 21 which is undoped. The polysilicon material 21 is formed on the insulation layer to fill up the trench groove. The top of the polysilicon material 21 is covered by an oxide film 22 which is formed by oxidation of the polysilicon material 21.
A first inter-layer insulator 12 is formed to cover an entire surface of the device. A second inter-layer insulator 13 is formed to cover an entire part of the first inter-layer insulator 12. The trench isolation 11 may be formed by etching from the field oxide film 5 to the upper portion of the semiconductor substrate 1.
A second typical conventional trench isolation is then described with reference to FIG. 2, wherein trench isolations 11 are provided to isolate a bipolar transistor from other regions. The bipolar transistor is formed over a p-type semiconductor substrate 1. An n-type buried layer 2 is formed on the p-type semiconductor substrate 1. An n-type epitaxial layer 3 is formed on the n-type buried layer 2. Field oxide films 5 are selectively formed in a surface of the n-type epitaxial layer 3 to define active regions interposed between them. Thin oxide films 16 are formed on the active regions the n-type epitaxial layer 3 serves as a collector region of the bipolar transistor. A collector plug region 6 is selectively formed in the n-type epitaxial region 3 on the other active region than the active region on which an emitter and a base are formed. A base region 7 comprising a p-type diffusion region is formed in an upper portion of the n-type epitaxial layer 3 under the thin oxide film on the active region. A base plug region 8 comprising a p-type diffusion region is formed in the upper portion of the n-type epitaxial layer 3, wherein the base plug region 8 is adjacent to and in contact with the base region 7. An emitter region 14 comprising an n-type diffusion region is formed in an upper portion of the p-type base region 7. The emitter region 14 is not covered by the thin oxide film 16, whilst the base region 7 and the base plug region 8 are covered by the thin oxide film 16. An emitter plug electrode 10 is formed on the emitter region 14.
The trench isolations 11 extend in a vertical direction from the field oxide film 5 through the n-type epitaxial layer 3 and the n-type buried layer 2 to an upper portion of the p-type semiconductor substrate 1. Each of the trench isolations 11 comprises a trench groove, an insulation film covering an inner wall of the trench groove and a polysilicon material 21 undoped. The polysilicon material 21 is provided to fill up the trench groove. The top of the polysilicon material 21 is covered by an oxide film which is formed by oxidation of the polysilicon material 21. At the bottom of each of the trench isolations 11, a channel stopper 4 comprising a p.sup.+ -region is formed. A first inter-layer insulator 9 is formed on an entire part of the device, except for an area on which the emitter plug electrode 10 resides. A second inter-layer insulator 12 is formed on an entire part of the device so that the second inter-layer insulator 12 covers the first inter-layer insulator 9 and the emitter plug electrode 10. A third inter-layer insulator 13 is formed on an entire surface of the second inter-layer insulator 12.
The trench isolations 11 isolate the collector region comprising a part of the epitaxial layer 3 from the other part of the epitaxial layer 3. This isolation of the collector region reduces a parasitic capacitance of the collector region with the buried layer 2. The reduction in the parasitic capacitance of the collector region with the buried layer 2 results in an improvement in high speed performance of the bipolar transistor such as increase in the switching speed thereof.
As a modification of the above conventional trench isolation, the trench groove may be filled with a boron phosphate silicate glass film (BPSG film) in place of the polysilicon material. The boron phosphate silicate glass film shows a fluidity when subjected to a heat treatment at a temperature in the range of 800-900.degree. C.
A third typical conventional trench isolation will be disclosed in Japanese laid-open Patent Application No. 3-149849, wherein the trench isolation has a top which is planarized. Fabrication processes of the trench groove will be described with reference to FIGS. 3A through 3D.
As illustrated in FIG. 3A, a thin oxide film 16 is formed on a surface of a semiconductor substrate 1. A field oxide film 5 is selectively formed by a local oxidation of silicon method using a mask made of silicon nitride. The silicon nitride mask is then removed. A silicon nitride film 17 having a thickness of 100 nanometers is deposited by a chemical vapor deposition method on an entire surface of the device to cover the filed oxide film 5 and the thin silicon oxide film 16. A phosphate silicate glass film 23 having a thickness of approximately 400 nanometers is then formed on an entire surface of the silicon nitride film 17. A photo-resist film is formed on an entire surface of the phosphate silicate glass film 23 and then patterned by a photo-lithography to form a photo-resist pattern having an opening which is positioned over a part of the field oxide film 5. A reactive ion etching is carried out by using the photo-resist pattern as a mask and using florin gas to selectively etch the phosphate silicate glass film 23, the silicon nitride film 17, and the field oxide film 5. The photo-=resist pattern is then removed. A reactive ion etching is again carried out by using the phosphate silicate glass film 23 having an opening as a mask and using a chlorine gas to selectively etch the semiconductor substrate 1 so that a trench groove 11 is formed extending in a vertical direction from the phosphate silicate glass film 23 to the semiconductor substrate 1.
As illustrated in FIG. 3B, the phosphate silicate glass film 23 is removed by a wet etching. Subsequently, the silicon nitride film 17 is used as a mask to an inner surface of the trench groove 11 to oxidation thereby forming a silicon oxide film 25 on the inner wall of the trench groove 11. A polysilicon film is deposited on an entire surface of the device to deposit over the silicon nitride film 17 and within the trench groove 11. The deposited polysilicon film over the silicon nitride film 17 is removed by etch back or polishing so that the polysilicon film remains only within the trench groove 11.
As illustrated in FIG. 3C, a silicate glass material is applied by a spin coating method on an entire surface of the device so that the silicate glass material is made flat and has a thickness of 100 nanometers. Subsequently, the applied silicate glass material is cured at a temperature of 800.degree. C. to form a silicate glass film 26 which covers an entire surface of the device. The substrate 1 is then placed in an oxygen atmosphere to cause oxygen to permeate through the silicate glass film 26 and reach the top of the polysilicon film 21 within the trench groove 11 so that an silicon oxide film 27 is formed at the top of the polysilicon film 21 within the trench groove 11. On the other hand, the silicon nitride film 17 prevents permeation of oxygen through itself. For this reason, the semiconductor substrate 1 which covered. by the silicon nitride film is not subjected to oxidation.
As illustrated in FIG. 3D, the silicate glass film 26 above the field oxide film 5 and the silicon nitride film 17 are removed by etching them to expose the field oxide film 5 and the thin film 16, provided that the silicate glass film 26 below the silicon nitride film 17 remains within the trench groove 11.
The above trench isolations have the following problems. First, a device is formed on a base layer which has a difference in level namely a step. With reference back to FIG. 3C, if etching of the silicate glass layer 26 is continued until the thin oxide film 16 is exposed, then the silicate glass layer 26 within the trench groove is also etched thereby resulting a recessed portion being formed within the trench groove. The recessed portion forms a step, namely has a difference in surface level. This cause is as follows. If the silicate glass is applied by a spin coating method, then the fluidity of the silicate glass causes that the silicate glass is deposited thickly on the thin oxide film 16 whilst the silicate glass is deposited thinly on the field oxide film 5. The thin oxide film 16 has the top which lies below the top of the field oxide film. For those reasons, if the silicate glass layer 26 is etched to expose the thin oxide film 16, then over etching of the silicate glass layer 26 on the field oxide film is caused. On the other hand, if the etching of the silicate glass layer 26 is stopped just when the top surface of the field oxide film 5 is exposed, then the silicate glass layer 26 remains only on the thin oxide film 16.
If the silicate glass 23 has the recessed portion namely the step at the top of the trench groove as described above and further a plurality of electrode patterns made of impurity-doped polysilicon is provided over the recessed portion or the step at the top of the trench groove, then the impurity-doped polysilicon would likely reside in the recessed portion in the dry etching process for patterning the electrodes. Such residual impurity-doped polysilicon in the recessed portion may likely cause any short circuit between the electrodes to be formed.
Further, if the width of the trench groove is reduced to obtain a scaling down of the device, then the following problems will be raised. With reference back to FIGS. 1 and 2, the oxide film 22 provided on the top of the trench isolation is formed by oxidation of the top of the polysilicon film 21. This oxidation is the thermal oxidation of silicon. The thermal oxidation causes thermal expansions of the top portion of the polysilicon film 21 and the oxide film. However, the thermal expansion coefficient of polysilicon differs from that of silicon oxide. This difference in thermal expansion coefficient between polysilicon and silicon oxide causes stresses at an interface between the field oxide film 5 and the epitaxial silicon layer underlying the field oxide film 5. Whereas such thermal stresses has both vertical and horizontal components, the horizontal component thereof is likely to be larger than the vertical component. Such stresses applied to the interface between the field oxide film 5 and the silicon layer may cause crystal defects at the interface between them. Particularly if the thickness of the oxide film 22 is large, for example, not less than 100 nanometers, then the crystal defects are likely caused. The crystal defects further cause crystal dislocations which extends along the interface between the field oxide film 5 and the silicon layer and may reach the diffusion regions acting as source/drain regions or the base regions. This results in remarkable deterioration in the device performances. This leads to a considerable reduction of the yield of the device manufacturing.
Whereas in the above descriptions, the trench groove is filled with the polysilicon material, a boron phosphate silicate glass film (BPSG film) and a phosphate silicate glass film (PSG film) are available to fill up the trench groove as disclosed in M. Sugiyama et al. 1989 Symp. VLSI, Dig. Paper, pp. 59-60. Fabrication processes are as illustrated in FIGS. 5A through 5C. The boron phosphate silicate glass film (BPSG film) and the phosphate silicate glass film (PSG film) generally show fluidity at a temperature of 900-950.degree. C. In this case, the boron phosphate silicate glass film (BPSG film) or the phosphate silicate glass film (PSG film) is formed on a surface having a step namely a difference in level, then the fabrication processes are similar to those in case of the silicate glass film illustrated in FIGS. 3C and 3D. For this reason, there are substantially the same problems. In other words, if the etching of the boron phosphate silicate glass film (BPSG film) or the phosphate silicate glass film (PSG film) is continued until the thin oxide film on the active region is exposed, then the boron phosphate silicate glass film (BPSG film) or the phosphate silicate glass film (PSG film) is over-etched thereby forming a recessed portion or a step at the top of the trench groove. FIG. 4A illustrates this problem with the recessed portion being formed over the top of a phosphate silicate glass film (PSG film) 28. If, however, the etching of the boron phosphate silicate glass film (BPSG film) or the phosphate silicate glass film (PSG film) is stopped just when the top surface of the field oxide film is exposed, then the boron phosphate silicate glass film (BPSG film) or the phosphate silicate glass film (PSG film) resides on the thin oxide film in the active region.
If the trench isolation comprises the trench groove filled with the boron phosphate silicate glass film (BPSG film) or the phosphate silicate glass film (PSG film), then the following problem is raised. Any heat treatment is normally carried out to form diffusion regions such as source/drain regions or base and emitter regions after the trench isolation is completely formed. Such heat treatment causes diffusions of boron and phosphorus atoms externally from the boron phosphate silicate glass film (BPSG film) or the phosphate silicate glass film (PSG film) within the trench groove. The diffused boron and phosphorus atoms act as impurities thereby causing variation in threshold voltage of the MOS transistor.
If the trench isolation comprises the trench groove filled with the boron phosphate silicate glass film (BPSG film) deposited by the chemical vapor deposition or filled with undoped polysilicon, then the following problem is raised. After filling the trench groove with those materials, a chemical treatment may often be carried out using a fluorine acid. The boron phosphate silicate glass film (BPSG film) and the undoped polysilicon film are etched by the fluorine acid base chemical. The etching rates thereof are larger than that of the thermal oxide film. For this reason, those materials within the trench groove may be removed partially or entirely.
In order to avoid the above problem, it is effective to form, as illustrated in FIG. 4B, a cap 24 made of etching-resistive material such as silicon nitride so that the cap 24 covers the top of the boron phosphate silicate glass film (BPSG film) and the undoped polysilicon film 28 within the trench groove 11. The cap 24 is formed by patterning process using photo-lithography. This increases the number of the fabrication processes.
The above trench isolation is available to isolate analog circuits from digital circuits, wherein the analog and digital circuits are formed on a single substrate, in order to prevent that digital noises generated by the digital circuits are propagated to the analog circuits as disclosed in Japanese laid-open Patent Application No. 3-178161. This trench isolation has substantially the same structure as described above. For this reason, such trench isolation may cause the same problem as described above.
Whereas in the above described prior art the trench isolation is formed after the field oxide film is formed, there is a different fabrication process, wherein the trench isolation is formed before the field oxide film is formed, as disclosed in 1990 J. Electrochem. Soc. Vol. 137, No. 6 pp. 1942-1950 "Planarized Deep-Trench Process fro Self-Aligned Double Polysilicon Bipolar Device Isolation". Fabrication processes are illustrated in FIGS. 6A through 6F which illustrate clearly that the trench isolation is formed before the field oxide film is formed over the top of the trench isolation. This isolation structure provides a flat surface of the field oxide film. There is no recessed portion nor step at the field oxide film over the trench isolation. Such isolation structure still has the following problems.
If the trench groove is filled with the insulating material containing any impurity, then the impurity diffusion externally from the trench isolation is caused by a heat treatment carried out for a device formation after the trench isolation and the field oxide film have been formed. As described above, the impurity diffusion externally from the trench isolation causes a variation in threshold voltage of the MOS transistor. Further in the LOCOS process for thermally growing the field oxide film, the field oxide film shows a different thermal expansion from that of the silicon epitaxial layer. This difference in thermal expansion between the silicon oxide film and the silicon epitaxial layer causes a stress at an interface between the silicon oxide film and the silicon epitaxial layer. The stress concentrates the field oxide film and the trench isolation. Whereas this thermal stress has horizontal and vertical components, the horizontal component is relatively larger than the vertical component. The thermal stress causes crystal defects at the interface between the field oxide film and the silicon epitaxial layer. This crystal defects cause a crystal dislocation which extends along the interface between the field oxide film and the silicon epitaxial layer and reaches the diffusion regions acting as source/drain regions. This causes a leakage current thereby resulting in a deterioration in device performance. The development of the novel trench isolation structure free from any of the above problems had been required.